
#include "user_custom.h"

	.equ	PDR_CA7,	0x4D022000
	.equ	DDR_CA7,	0x4D022100
	.equ	EPCR_CA7,	0x4D022200
	.equ	PUDER_CA7,	0x4D022300
	.equ	PUDCR_CA7,	0x4D022400

	.equ	PDR_CM0,	0x4DFFB000
	.equ	DDR_CM0,	0x4DFFB100
	.equ	EPCR_CM0,	0x4DFFB200
	.equ	PUDER_CM0,	0x4DFFB300
	.equ	PUDCR_CM0,	0x4DFFB400

	.equ	CRPLC,		0x4DFFE000
	.equ	CRSTP,		0x4DFFE008
	.equ	CRRSC,		0x4DFFE020
	.equ	CRSWR_CM0,	0x4DFFE024
	.equ	CRRSM,		0x4DFFE02C
	.equ	CRCDC,		0x4DFFE030
	.equ	CRDM,		0x4DFFE100
	.equ	CRLP,		0x4DFFE104

	.equ	CLKSEL,		0x4D021000
	.equ	PLLCNTL,	0x4D021030
	.equ	CLKSTOP,	0x4D021054
	.equ	CRSWR_CA7,	0x4D02108C
	.equ	CRRRS,		0x4D021090
	.equ	PLLFREQ1,	0x4D023000
	.equ	ODIVCH0,	0x4D023040
	.equ	CMDEN,		0x4D023080

	.equ	PERSEL3,	0x4D020008
	.equ	PERSEL4,	0x4D02000C

	.equ	PERSELM1,	0x4DFF4004

	.text
	.thumb
	.thumb_func
	.align 1
	
	.type vStartupHW, %function
	.global	vStartupHW
	
	.macro WR_W	addr, val
	ldr	r0, =\addr
	ldr	r1, =\val
	str	r1, [r0]
	.endm

	.macro WAIT_BY_COUNT	count
// 1usec ---> count=50
//     CM0 clock 100MHz
//     2 instructions/loop ---> 50MHz, 20nsec/ins
	ldr	r0, =\count
1:
	sub		r0, #1
	cmp		r0, #0
	bne		1b
	.endm

vStartupHW:

//--------------------------------------------------------------------------
// IO setting
//--------------------------------------------------------------------------
	// PUDCR
	WR_W	PUDCR_CM0,			0x00000000		// PUDCR10 -> PUDCR1[15:8], PUDCR0[7:0].
	WR_W	(PUDCR_CM0 + 0x04),	0x00000000		// PUDCR32
	WR_W	(PUDCR_CM0 + 0x08),	0x00000000		// PUDCR54

	WR_W	(PUDCR_CA7 + 0x0C),	0x00000000		// PUDCR76
	WR_W	(PUDCR_CA7 + 0x10),	0x00000000		// PUDCR98
	WR_W	(PUDCR_CA7 + 0x14),	0x00000200		// PUDCRBA
	WR_W	(PUDCR_CA7 + 0x18),	0x00000800		// PUDCRDC
#if defined(BOARD_TYPE_SNI_SMALL)
	WR_W	(PUDCR_CA7 + 0x1C),	0x00000000		// PUDCRFE
#else	/* BOARD_TYPE_SNI_SMALL */
	WR_W	(PUDCR_CA7 + 0x1C),	0x00000400		// PUDCRFE
#endif	/* BOARD_TYPE_SNI_SMALL */
	WR_W	(PUDCR_CA7 + 0x20),	0x00000000		// PUDCRHG
	WR_W	(PUDCR_CA7 + 0x24),	0x00000000		// PUDCRJW
	WR_W	(PUDCR_CA7 + 0x28),	0x00000000		// PUDCRLK
	WR_W	(PUDCR_CA7 + 0x2C),	0x00000000		// PUDCRNM
	WR_W	(PUDCR_CA7 + 0x30),	0x00000300		// PUDCRPY

	// PUDER
#if defined(BOARD_TYPE_SNI_SMALL)
	WR_W	PUDER_CM0,			0x000020E0		// PUDER10
	WR_W	(PUDER_CM0 + 0x04),	0x00000DCF		// PUDER32
	WR_W	(PUDER_CM0 + 0x08),	0x00000000		// PUDER54

	WR_W	(PUDER_CA7 + 0x0C),	0x00003E08		// PUDER76
	WR_W	(PUDER_CA7 + 0x10),	0x00000CBA		// PUDER98
	WR_W	(PUDER_CA7 + 0x14),	0x00000270		// PUDERBA
	WR_W	(PUDER_CA7 + 0x18),	0x00006830		// PUDERDC
	WR_W	(PUDER_CA7 + 0x1C),	0x00001F0C		// PUDERFE
	WR_W	(PUDER_CA7 + 0x20),	0x00000E00		// PUDERHG
	WR_W	(PUDER_CA7 + 0x24),	0x0000FFFF		// PUDERJW
	WR_W	(PUDER_CA7 + 0x28),	0x00003FFF		// PUDERLK
	WR_W	(PUDER_CA7 + 0x2C),	0x00001010		// PUDERNM
	WR_W	(PUDER_CA7 + 0x30),	0x000003FF		// PUDERPY
#else	/* BOARD_TYPE_SNI_SMALL */
	WR_W	PUDER_CM0,			0x000000E0		// PUDER10 -> PUDER1[15:8], PUDER0[7:0].
	WR_W	(PUDER_CM0 + 0x04),	0x00000008		// PUDER32
	WR_W	(PUDER_CM0 + 0x08),	0x00000000		// PUDER54

	WR_W	(PUDER_CA7 + 0x0C),	0x00002000		// PUDER76
	WR_W	(PUDER_CA7 + 0x10),	0x000000BE		// PUDER98
	WR_W	(PUDER_CA7 + 0x14),	0x00000200		// PUDERBA
	WR_W	(PUDER_CA7 + 0x18),	0x00000800		// PUDERDC
	WR_W	(PUDER_CA7 + 0x1C),	0x00001C00		// PUDERFE
	WR_W	(PUDER_CA7 + 0x20),	0x00000E38		// PUDERHG
	WR_W	(PUDER_CA7 + 0x24),	0x00000000		// PUDERJW
	WR_W	(PUDER_CA7 + 0x28),	0x000030FC		// PUDERLK
	WR_W	(PUDER_CA7 + 0x2C),	0x00001010		// PUDERNM
	WR_W	(PUDER_CA7 + 0x30),	0x00000300		// PUDERPY
#endif	/* BOARD_TYPE_SNI_SMALL */

	// EPCR
	WR_W	EPCR_CM0,			0x00000000		// EPCR10 -> EPCR1[15:8], EPCR0[7:0].
	WR_W	(EPCR_CM0 + 0x04),	0x00000000		// EPCR32
#if UART_TYPE == UART_TYPE_NO_USE
	WR_W	(EPCR_CM0 + 0x08),	0x00000000		// EPCR54
#else	/* UART_TYPE */
	WR_W	(EPCR_CM0 + 0x08),	0x00000020		// EPCR54
#endif	/* UART_TYPE */

	WR_W	(EPCR_CA7 + 0x0C),	0x00000000		// EPCR76
#if defined(BOARD_TYPE_SNI_SMALL)
	WR_W	(EPCR_CA7 + 0x10),	0x00000100		// EPCR98
	WR_W	(EPCR_CA7 + 0x14),	0x00001F8B		// EPCRBA
	WR_W	(EPCR_CA7 + 0x18),	0x00001F0F		// EPCRDC
	WR_W	(EPCR_CA7 + 0x1C),	0x00000022		// EPCRFE
	#if defined(ETHER_EN)
	WR_W	(EPCR_CA7 + 0x20),	0x000001F7		// EPCRHG
	#else
	WR_W	(EPCR_CA7 + 0x20),	0x00000107		// EPCRHG
	#endif
	WR_W	(EPCR_CA7 + 0x24),	0x00000000		// EPCRJW
	WR_W	(EPCR_CA7 + 0x28),	0x00000000		// EPCRLK
	WR_W	(EPCR_CA7 + 0x2C),	0x00000212		// EPCRNM
	WR_W	(EPCR_CA7 + 0x30),	0x00000C00		// EPCRPY
#else	/* BOARD_TYPE_SNI_SMALL */
	WR_W	(EPCR_CA7 + 0x10),	0x000005B0		// EPCR98
	WR_W	(EPCR_CA7 + 0x14),	0x00001FAB		// EPCRBA
	WR_W	(EPCR_CA7 + 0x18),	0x00007F3F		// EPCRDC
	WR_W	(EPCR_CA7 + 0x1C),	0x0000002A		// EPCRFE
	#if defined(ETHER_EN)
	WR_W	(EPCR_CA7 + 0x20),	0x00000130		// EPCRHG
	#else
	WR_W	(EPCR_CA7 + 0x20),	0x00000107		// EPCRHG
	#endif
	WR_W	(EPCR_CA7 + 0x24),	0x0000FFFF		// EPCRJW
	WR_W	(EPCR_CA7 + 0x28),	0x00000F03		// EPCRLK
	WR_W	(EPCR_CA7 + 0x2C),	0x00000212		// EPCRNM
	WR_W	(EPCR_CA7 + 0x30),	0x00000CF3		// EPCRPY
#endif	/* BOARD_TYPE_SNI_SMALL */

	// PDR
	WR_W	PDR_CM0,			0xFFFF0002		// PDR10 -> PDRWE1[31:24], PDRWE0[23:16], PDR1[15:8], PDR0[7:0].
#if defined(BOARD_TYPE_SNI_SMALL)
#ifdef BOOT_LED
	WR_W	(PDR_CM0 + 0x04),	0xFFFF0000		// PDR32
#else
	WR_W	(PDR_CM0 + 0x04),	0xFFFF0000		// PDR32
#endif
	WR_W	(PDR_CM0 + 0x08),	0x00700000		// PDR54

	WR_W	(PDR_CA7 + 0x0C),	0xFFFF0134		// PDR76
	WR_W	(PDR_CA7 + 0x10),	0x0FFF0040		// PDR98
	WR_W	(PDR_CA7 + 0x14),	0x1FFF0000		// PDRBA
	WR_W	(PDR_CA7 + 0x18),	0x7F3F0000		// PDRDC
	WR_W	(PDR_CA7 + 0x1C),	0x1F3F0000		// PDRFE
	#if defined(ETHER_EN)
	WR_W	(PDR_CA7 + 0x20),	0x0FFF0008		// PDRHG
	#else
	WR_W	(PDR_CA7 + 0x20),	0x0FFF0000		// PDRHG
	#endif
	WR_W	(PDR_CA7 + 0x24),	0xFFFF0000		// PDRJW
	WR_W	(PDR_CA7 + 0x28),	0x3FFF0000		// PDRLK
	WR_W	(PDR_CA7 + 0x2C),	0x1F1F0000		// PDRNM
	WR_W	(PDR_CA7 + 0x30),	0x0F000000		// PDRPY
#else	/* BOARD_TYPE_SNI_SMALL */
#ifdef BOOT_LED
	WR_W	(PDR_CM0 + 0x04),	0xFFEF0100		// PDR32
#else
	WR_W	(PDR_CM0 + 0x04),	0xFFFF0100		// PDR32
#endif
	WR_W	(PDR_CM0 + 0x08),	0x00700000		// PDR54

	WR_W	(PDR_CA7 + 0x0C),	0xFFFF1F30		// PDR76
	WR_W	(PDR_CA7 + 0x10),	0x0FFF0040		// PDR98
	WR_W	(PDR_CA7 + 0x14),	0x0FFF0000		// PDRBA
	WR_W	(PDR_CA7 + 0x18),	0x7F3F0000		// PDRDC
	WR_W	(PDR_CA7 + 0x1C),	0x1F3F0400		// PDRFE
	#if defined(ETHER_EN)
	WR_W	(PDR_CA7 + 0x20),	0x0FFF0008		// PDRHG
	#else
	WR_W	(PDR_CA7 + 0x20),	0x0FFF0000		// PDRHG
	#endif
	WR_W	(PDR_CA7 + 0x24),	0xFFFF0000		// PDRJW
	WR_W	(PDR_CA7 + 0x28),	0x3FFF0000		// PDRLK
	WR_W	(PDR_CA7 + 0x2C),	0x1F1F0000		// PDRNM
	WR_W	(PDR_CA7 + 0x30),	0x0FFF0000		// PDRPY
#endif	/* BOARD_TYPE_SNI_SMALL */

	// DDR
	WR_W	DDR_CM0,			0x00000002		// DDR10 -> DDR1[15:8], DDR0[7:0].
#if defined(BOARD_TYPE_SNI_SMALL)
#ifdef BOOT_LED
	WR_W	(DDR_CM0 + 0x04),	0x00000030		// DDR32
#else
	WR_W	(DDR_CM0 + 0x04),	0x00000030		// DDR32
#endif
#if UART_TYPE == UART_TYPE_NO_USE
	WR_W	(DDR_CM0 + 0x08),	0x00000040		// DDR54
#else	/* UART_TYPE */
	WR_W	(DDR_CM0 + 0x08),	0x00000060		// DDR54
#endif	/* UART_TYPE */

	WR_W	(DDR_CA7 + 0x0C),	0x00000137		// DDR76
	WR_W	(DDR_CA7 + 0x10),	0x00000145		// DDR98
	WR_W	(DDR_CA7 + 0x14),	0x0000038B		// DDRBA
	WR_W	(DDR_CA7 + 0x18),	0x00001E00		// DDRDC
	WR_W	(DDR_CA7 + 0x1C),	0x00000022		// DDRFE
	#if defined(ETHER_EN)
	WR_W	(DDR_CA7 + 0x20),	0x000001CF		// DDRHG
	#else
	WR_W	(DDR_CA7 + 0x20),	0x00000107		// DDRHG
	#endif
	WR_W	(DDR_CA7 + 0x24),	0x00000000		// DDRJW
	WR_W	(DDR_CA7 + 0x28),	0x00000000		// DDRLK
	WR_W	(DDR_CA7 + 0x2C),	0x00000212		// DDRNM
	WR_W	(DDR_CA7 + 0x30),	0x00000C00		// DDRPY
#else	/* BOARD_TYPE_SNI_SMALL */
#ifdef BOOT_LED
	WR_W	(DDR_CM0 + 0x04),	0x0000017F		// DDR32
#else
	WR_W	(DDR_CM0 + 0x04),	0x0000011F		// DDR32
#endif
#if UART_TYPE == UART_TYPE_NO_USE
	WR_W	(DDR_CM0 + 0x08),	0x00000040		// DDR54
#else	/* UART_TYPE */
	WR_W	(DDR_CM0 + 0x08),	0x00000060		// DDR54
#endif	/* UART_TYPE */

	WR_W	(DDR_CA7 + 0x0C),	0x00001F3F		// DDR76
	WR_W	(DDR_CA7 + 0x10),	0x000005F1		// DDR98
	WR_W	(DDR_CA7 + 0x14),	0x000003AB		// DDRBA
	WR_W	(DDR_CA7 + 0x18),	0x00007E00		// DDRDC
	WR_W	(DDR_CA7 + 0x1C),	0x00001C2A		// DDRFE
	#if defined(ETHER_EN)
	WR_W	(DDR_CA7 + 0x20),	0x00000108		// DDRHG
	#else
	WR_W	(DDR_CA7 + 0x20),	0x00000107		// DDRHG
	#endif
	WR_W	(DDR_CA7 + 0x24),	0x0000FFFF		// DDRJW
	WR_W	(DDR_CA7 + 0x28),	0x00002F03		// DDRLK
	WR_W	(DDR_CA7 + 0x2C),	0x00000212		// DDRNM
	WR_W	(DDR_CA7 + 0x30),	0x00000C00		// DDRPY
#endif	/* BOARD_TYPE_SNI_SMALL */

//--------------------------------------------------------------------------
// CLOCK setting
//--------------------------------------------------------------------------
	// CM0
	// Set CLK0 - CLK5 (CLK2:No Use)
	WR_W	CRDM,				0x00000000		// CRDM0.DIVMODE0=0.
	WR_W	CRLP,				0xFF0000FF		// CRLP0.CEN0=0xFF, CRLP0.CSYSREQ_R0=0xFF.
	WR_W	(CRDM + 0x10),		0x00000001		// CRDM1.DIVMODE0=1
	WR_W	(CRLP + 0x10),		0xFF0000FF		// CRLP1.CEN1=0xFF, CRLP1.CSYSREQ_R1=0xFF.
	WR_W	(CRDM + 0x30),		0x00000001		// CRDM3.DIVMODE0=1
	WR_W	(CRLP + 0x30),		0xFF0000FF		// CRLP3.CEN3=0xFF, CRLP3.CSYSREQ_R3=0xFF.
	WR_W	(CRDM + 0x40),		0x00000001		// CRDM4.DIVMODE0=1
	WR_W	(CRLP + 0x40),		0xFF0000FF		// CRLP4.CEN4=0xFF, CRLP4.CSYSREQ_R4=0xFF.
	WR_W	(CRDM + 0x50),		0x00000001		// CRDM5.DIVMODE0=1
	WR_W	(CRLP + 0x50),		0xFF0000FF		// CRLP5.CEN5=0xFF, CRLP5.CSYSREQ_R5=0xFF.
	// Update clock divider mode
	WR_W	CRCDC,				0x00000001		// DCHREQ=1.

	// CA7
	// Set CLKSELx
#ifndef CO_POWER_MEASUREMENT
	WR_W	CLKSEL,				0x48231884		// CLKSEL1
#else
	WR_W	CLKSEL,				0x48225884		// CLKSEL1
#endif
	WR_W	(CLKSEL + 0x04),	0x488888C8		// CLKSEL2
// ###   DELETE_ES3 BEGIN
#ifdef CO_ES3_HARDWARE
// ###   DELETE_ES3 END
	WR_W	(CLKSEL + 0x08),	0x54511488		// CLKSEL3
// ###   DELETE_ES3 BEGIN
#endif
// ###   DELETE_ES3 END
// ###   DELETE_ES1 BEGIN
#ifdef CO_ES1_HARDWARE
// ###   DELETE_ES1 END
	WR_W	(CLKSEL + 0x08),	0x14511488		// CLKSEL3
// ###   DELETE_ES1 BEGIN
#endif
// ###   DELETE_ES1 END
	WR_W	(CLKSEL + 0x0C),	0x88102040		// CLKSEL4
	WR_W	(CLKSEL + 0x10),	0x00010820		// CLKSEL5
	WR_W	(CLKSEL + 0x14),	0x88102040		// CLKSEL6
// ###   DELETE_ES3 BEGIN
#ifdef CO_ES3_HARDWARE
// ###   DELETE_ES3 END
	WR_W	(CLKSEL + 0x18),	0x01250820		// CLKSEL7
// ###   DELETE_ES3 BEGIN
#endif
// ###   DELETE_ES3 END
// ###   DELETE_ES1 BEGIN
#ifdef CO_ES1_HARDWARE
// ###   DELETE_ES1 END
	WR_W	(CLKSEL + 0x18),	0x00010820		// CLKSEL7
// ###   DELETE_ES1 BEGIN
#endif
// ###   DELETE_ES1 END
	WR_W	(CLKSEL + 0x1C),	0x554155A4		// CLKSEL8
	WR_W	(CLKSEL + 0x20),	0x00BBBBCF		// CLKSEL9
	WR_W	(CLKSEL + 0x24),	0x000002DD		// CLKSEL10
// ###   DELETE_ES1 BEGIN
#ifdef CO_ES1_HARDWARE
// ###   DELETE_ES1 END
#ifdef BOARD_TYPE_SNI_SMALL
	WR_W	(CLKSEL + 0x28),	0x00000001		// CLKSEL11
#endif	/* BOARD_TYPE_SNI_SMALL */
// ###   DELETE_ES1 BEGIN
#endif
// ###   DELETE_ES1 END
// ###   DELETE_ES3 BEGIN
#ifdef CO_ES3_HARDWARE
// ###   DELETE_ES3 END
	WR_W	(CLKSEL + 0x2C),	0x42148812		// CLKSEL12
// ###   DELETE_ES3 BEGIN
#endif
// ###   DELETE_ES3 END
// ###   DELETE_ES1 BEGIN
#ifdef CO_ES1_HARDWARE
// ###   DELETE_ES1 END
	WR_W	(CLKSEL + 0x2C),	0x22148812		// CLKSEL12
// ###   DELETE_ES1 BEGIN
#endif
// ###   DELETE_ES1 END
	// Set PLLCNTLx
	WR_W	(PLLCNTL + 0x08),	0x003400C7		// PLLCNTL3
	WR_W	(PLLCNTL + 0x0C),	0x00000000		// PLLCNTL4
	WR_W	(PLLCNTL + 0x10),	0x00000000		// PLLCNTL5
	WR_W	(PLLCNTL + 0x14),	0x00000000		// PLLCNTL6
#ifndef CO_POWER_MEASUREMENT
	WR_W	(PLLCNTL + 0x18),	0x005C0311		// PLLCNTL7
	WR_W	(PLLCNTL + 0x1C),	0x000C0007		// PLLCNTL8
#else
	WR_W	(PLLCNTL + 0x18),	0x001D0022		// PLLCNTL7
	WR_W	(PLLCNTL + 0x1C),	0x003E041D		// PLLCNTL8
#endif
	WR_W	(PLLCNTL + 0x20),	0x00004A00		// PLLCNTL9
	WR_W	PLLCNTL,			0x000017FF		// PLLCNTL1
	
	WAIT_BY_COUNT 20000
	
	WR_W	(PLLCNTL + 0x04),	0x000017FF		// PLLCNTL2
#ifndef CO_POWER_MEASUREMENT
	WR_W	PLLCNTL,			0x0006F7FF		// PLLCNTL1
#else
	WR_W	PLLCNTL,			0x0006F58E		// PLLCNTL1
#endif
	
	WAIT_BY_COUNT 20000
	
	// Set CLKSTOPx
#ifndef CO_POWER_MEASUREMENT
//	WR_W	CLKSTOP,			0x33FFFFFF		// CLKSTOP1
#else
	WR_W	CLKSTOP,			0x03000000		// CLKSTOP1
#endif
//	WR_W	(CLKSTOP + 0x04),	0xFFFFEAAA		// CLKSTOP2
#ifndef CO_POWER_MEASUREMENT
//	WR_W	(CLKSTOP + 0x08),	0xFFFFFFFF		// CLKSTOP3
#else
	WR_W	(CLKSTOP + 0x08),	0xF0000000		// CLKSTOP3
#endif
//	WR_W	(CLKSTOP + 0x0C),	0xFFFFFFFF		// CLKSTOP4
//	WR_W	(CLKSTOP + 0x10),	0x3FFFFFFF		// CLKSTOP5
//	WR_W	(CLKSTOP + 0x14),	0x3FFCFFFF		// CLKSTOP6
//	WR_W	(CLKSTOP + 0x18),	0x3F3FFFFF		// CLKSTOP7
//	WR_W	(CLKSTOP + 0x1C),	0xFFFFFFFF		// CLKSTOP8
//	WR_W	(CLKSTOP + 0x20),	0x2BFFFFFF		// CLKSTOP9
//	WR_W	(CLKSTOP + 0x24),	0x3FFFFFFF		// CLKSTOP10
//	WR_W	(CLKSTOP + 0x28),	0x2AFFFFFF		// CLKSTOP11
//	WR_W	(CLKSTOP + 0x2C),	0x3FFFFFFF		// CLKSTOP12
//	WR_W	(CLKSTOP + 0x30),	0xFFFFFFFF		// CLKSTOP13
//	WR_W	(CLKSTOP + 0x34),	0xFCFEBFFF		// CLKSTOP14
	// Set CRSWR/CRRRS
	WR_W	CRSWR_CA7,			0x00000000		// CRSWR
	WR_W	CRRRS,				0x0000003F		// CRRRS
	// Set PLL09 Control
	WR_W	PLLFREQ1,			0x0000002D		// PLLFREQ1
	WR_W	CMDEN,				0x00000004		// CMDEN : reflect the settings to PLLFREQ1
	WR_W	ODIVCH0,			0x00000101		// ODIVCH0
	WR_W	CMDEN,				0x00000002		// CMDEN : reflect the settings to ODIVCH0

	// Set PERSEL3
#if defined(ETHER_EN)
	WR_W	PERSEL3,			0x00200000		// bit21=1:NIMDC(Management Data clock output)
#else
	WR_W	PERSEL3,			0x00000000		// bit21=0(SNAPCLK1 or GPIO)
#endif
	
	// Set PERSEL4
	WR_W	PERSEL4,			0x00000000
	
	// PERSELM1
	WR_W	PERSELM1,			0x0000CC00		// SP0CSUDC/SP0SCKUDC/SP0CSPE/SP0SCKPE=1
	
	bx	lr

//--------------------------------------------------------------------------
// EXS setting
//--------------------------------------------------------------------------
	.type vStartupHW_EXS, %function
	.global	vStartupHW_EXS
vStartupHW_EXS:
	bx	lr
	
    .end
